In manufacture of Large Scale Integrated Circuits, generally a dielectric spacer is formed before a Light Doped Drain (LDD) implantation process, to prevent source/drain implantation at a greater dose from being too close to a channel to cause source-drain punch-through, which in turn results in device failure and a reduced yield.
Presently, a popular 65 nm node spacer or even a 45 nm node spacer can be fabricated as follows. Before the LDD implantation process, a thin film layer of silicon oxide is deposited or thermally grown. For example, the layer of silicon oxide can be grown by means of Rapid Thermal Oxidation (RTO) to a thickness of about 30 Å, and then can serve as an etching stop layer for protecting a substrate, especially interfaces of source/drain regions close to a channel region, from damages, to avoid increase of defect densities. Further, a well conformal thin film layer of silicon nitride is deposited to surround a polysilicon gate. Finally, portions of the silicon nitride on the substrate and the gate can be removed away by means of plasma etching, which is stopped on the underlying oxide layer. As a result, the spacer is achieved.
On the other hand, as critical dimensions are continuously scaling down according to the Moore's Law, the conventional gate oxide/polysilicon gate configuration is going further away from requirements of advanced logic devices, and thus is being replaced gradually by the high K-metal gate configuration. Further, the gate last process is becoming a dominant one because of its good control of thermal effects and threshold voltages, but causes many new difficulties and challenges. For a first spacer, if it is manufactured by the conventional process where the combination of silicon oxide and silicon nitride is adopted, then silicon nitride will react with the high K dielectric, resulting in a reduced K value and thus an increased Effective Oxide Thickness (EOT). Due to this, a gate control capability is degraded, and an on-off ratio is deteriorated. Further, the gate should have a reduced height, to cope with the challenge of filling the metal gate occurring in the development of the CMOS manufacture processes. To fill the metal in a solid manner, it is necessary to reduce a depth-to-width ratio of a gate line. Furthermore, due to continuous scaling of a gate pitch, the thickness of the first spacer is continuously decreasing. To precisely control the repeatability, reliability, and stability of the etching process, it is necessary to slow down an etching rate to fight with increasingly stringent challenges of the etching process. This tends to deteriorate the uniformity of the etching rate of the spacer. Especially, current spacer etching techniques are generally based on Ar-based gases, which tend to make damages to the substrate, particularly for nanometer-scale devices.